[Python] Inheritance

Python is an object-oriented programming language, so it also has inheritance, overloading, overriding, etc. Below is one of the simple examples of how inheritance is implemented in Python.

By looking at below example, it is easy to learn how a class inherits from other classes and how a class is declared, defined and used in Python.

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Python là một ngôn ngữ lập trình hướng đối tượng! bên dưới là một ví dụ đơn giản về tính thừa kế trong Python.

[Basic VHDL] Wait Statements

Wait statement is one of the useful statements in VHDL. we can use it for either synthesizable or non-synthesizable code. Below are 3 main syntax for wait statement:

+ wait until condition
 For example: wait until i_clk_sl'event and i_clk_sl = '1';

[Basic VHDL] Basic difference between signal and variable

There are some differences between signal and variable, but we just need to keep in mind the following basic differences:
+ Variables can only be used inside processes
+ Variables are assigned using the := assignment symbol; signals are assigned using the <= assignment symbol.
+ variables immediately take the value of their assignment; but, signal is going to take the value at the next clock cycle.

[Basic VHDL] Concatenation operator

Concatenation operator is very useful in VHDL when we want to do the shift logic.

Its syntax: A & B

Example:

[Basic VHDL] Type Conversion / Chuyển đổi kiểu dữ liệu

1- Automatic Type conversion:
Elements of signed, unsigned, and std_logic_vector can be converted automatically to std_ulogic or std_logic.

For example,

x1_std_logic <= y1_std_logic_vector(1);
x2_std_logic <= y2_unsigned(3);

[Basic VHDL] Fully Synchronous counter ( Bộ cộng đồng bộ 8 bít )

Here, we implement a 8-bit counter which has 4 controls input: clear, load, enable, and carry. All the states can be changed at the rising clock edge.

Specification:
if clear = 1 => the output is reset to 0;
if load = 1 => the input will be loaded to the output q;
if enable = 1 and carry = 1 => the output will be increased at every single clk.
      => if carry =1, then the carry out Cout will be calculated.

[Basic VHDL] arithmetic operation

One of the common errors that many beginners will experience at the first time when they use vhdl is:: ERROR:HDLCompiler:1731 which means that : found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+". Let see what the root cause of this error is and how to fix it:

In VHDL, we cannot use arithmetic operation on std_logic or std_logic_vector data type directly. Let consider below code snippet:

[Basic VHDL] Type Conversion Functions

VHDL is a very strong-type language, it means that we must supply the arguments of exactly right type to a function or operator. Otherwise, the compiler will give an error message.

Although many functions or operators are overloaded so that you can use the same functions for more than one type of data, in many cases it is a must to do a type conversion.

Many type conversions can be found in the package std_logic_arith in ieee library. Mostly we deal with std_logic_vector, unsigned and integer type.

Below are some common conversion functions, we should memorize because of its convenience:

std_logic_vector to  unsigned: unsigned(x)

std_logic_vector to integer: conv_integer(x)

unsigned to std_logic_vector: std_logic_vector(x)

unsigned to integer: conv_integer(x)

integer to unsigned: conv_unsigned(x,len)

integer to std_logic_vector: conv_std_logic_vector(x,leng)

std_logic_vector to integer: to_integer(unsigned(x));


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[Xilinx] Simulation Runtime: How to change default simulation run time

Default simulation run time in Xilinx is 1000ns. Sometimes, we need a bigger time frame to run our simulation. We can easily change this default value into our desired value. It can be done either by ISIM command or window GUI setting.

Below is one of the easy ways to change default simulation run time. ( simulation time )


Step1: From your main working workspace, choose the option "Simulation"

(Click The Image To Enlarge The View)

Step 2: Right click on Simulate Behavioral Model, then choose Process Properties...

(Click The Image To Enlarge The View)

Step 3 : change the default vaule 1000 ns in texbox Simulation Run Time to your expected value:

 

(Click The Image To Enlarge The View)

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[Basic VHDL] Signal Assignments: with/select ; when/else; case/when

In  vhdl, we usually can do the same things in different ways; and, signal assignment is one of the them. There are basically 3 ways to do it. They are look kinda similar and not easy to remember. Let's take a look at these signal assignments.

1- with .... select ..... when
with/select is called officially "selected signal assignment" in vhdl. below is an example of this signal assignment:

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with op select controls y <= "110000010" when "000000", "101001000" when "100011", "001010000" when "101011", "000100001" when "000100", "101000000" when "001000", "000000100" when "000010", "---------" when others;

2- When ..... else
It is officially called "conditional signal assignment"  in vhdl. It seems to be a little bit more general than with/select/when. Below is an example of this signal assignment:

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y <= "110000010" when op = "000000" else "101001000" when op = "100011" else "001010000" when op = "101011" else "000100001" when op = "000100" else "101000000" when op = "001000" else "000000100" when op = "000010" else "---------" when others;

3- Case ... when
This statement is always used inside a process. This statement is the same as IF-THEN-ELSE statement. They are equivalent.

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process(op) is begin case op is when "000000" => controls <= "110000010"; when "100011" => controls <= "101001000"; when "101011" => controls <= "001010000"; when "000100" => controls <= "000100001"; when "001000" => controls <= "101000000"; when "000010" => controls <= "000000100"; when others => controls <= "---------"; end case; end process;

[Xilinx] Error Fixing: model technology's vsim executable cannot be found

Whenever you have got below error while running simulation:
"model technology's vsim executable cannot be found"

It means that you need to choose a suitable simulator, there are some ways to overcome this. below is one of the easy way to fix this error ( for VHDL ):

Step1: Right click on your main file, and choose Design Properties...:

Step2: a new window will be popped up. Then click on Simulator, then choose ISim as below image:

 

That is it! try to run your simulation again!