[Basic VHDL] Wait Statements

Wait statement is one of the useful statements in VHDL. we can use it for either synthesizable or non-synthesizable code. Below are 3 main syntax for wait statement:

+ wait until condition
 For example: wait until i_clk_sl'event and i_clk_sl = '1';

[Basic VHDL] Basic difference between signal and variable

There are some differences between signal and variable, but we just need to keep in mind the following basic differences:
+ Variables can only be used inside processes
+ Variables are assigned using the := assignment symbol; signals are assigned using the <= assignment symbol.
+ variables immediately take the value of their assignment; but, signal is going to take the value at the next clock cycle.

[Basic VHDL] Concatenation operator

Concatenation operator is very useful in VHDL when we want to do the shift logic.

Its syntax: A & B

Example:

[OOP] Function Poniters/ con trỏ hàm

Below is a note which demonstrates how to declare and use function pointers.
 (VN version: Ví dụ đơn giản về con trỏ hàm: cách khai báo, cách gọi con trỏ hàm)

[Basic VHDL] Type Conversion / Chuyển đổi kiểu dữ liệu

1- Automatic Type conversion:
Elements of signed, unsigned, and std_logic_vector can be converted automatically to std_ulogic or std_logic.

For example,

x1_std_logic <= y1_std_logic_vector(1);
x2_std_logic <= y2_unsigned(3);

[Basic VHDL] Fully Synchronous counter ( Bộ cộng đồng bộ 8 bít )

Here, we implement a 8-bit counter which has 4 controls input: clear, load, enable, and carry. All the states can be changed at the rising clock edge.

Specification:
if clear = 1 => the output is reset to 0;
if load = 1 => the input will be loaded to the output q;
if enable = 1 and carry = 1 => the output will be increased at every single clk.
      => if carry =1, then the carry out Cout will be calculated.