[Basic VHDL] Wait Statements

Wait statement is one of the useful statements in VHDL. we can use it for either synthesizable or non-synthesizable code. Below are 3 main syntax for wait statement:

+ wait until condition
 For example: wait until i_clk_sl'event and i_clk_sl = '1';


+ wait on sensitivity list
 For example: wait on i_clk_sl;

+ wait for time expression 
For example: wait for 10 ns


 One thing we need to keep in mind is that: Process cannot have both a wait statement and a sensitivity list.

In the third wait statement, if we don't have a specific time, then the process will wait there forever. And, this wait statement cannot be synthesizable.

Example Code

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity wait_cmd_test is port( i_input_sl: in std_logic; i_clk_sl: in std_logic; o_output_sl: out std_logic ); end wait_cmd_test; architecture Behavioral of wait_cmd_test is begin PRO_WAIT_TEST: process is begin wait until i_clk_sl'event and i_clk_sl = '1'; o_output_sl <= i_clk_sl; end process PRO_WAIT_TEST; end Behavioral;