[Basic VHDL] Concatenation operator

Concatenation operator is very useful in VHDL when we want to do the shift logic.

Its syntax: A & B

Example:

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LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; --mathhoang ENTITY test IS port( i_a_sl: in std_logic; i_b_sl: in std_logic; o_b_slv: out std_logic_vector(1 downto 0) ); END test; ARCHITECTURE behavior OF test IS signal r_VAL_1_sl: std_logic := '0'; signal r_VAL_2_sl: std_logic := '0'; signal r_RESULT_int: integer range 0 to 3 := 0; BEGIN P_CONCATENATE: process(r_VAL_1_sl, r_VAL_2_sl) variable v_CONCATENATE_slv: std_logic_vector(1 downto 0); begin v_CONCATENATE_slv := r_VAL_1_sl & r_VAL_2_sl; case v_CONCATENATE_slv is when "00" => r_RESULT_int <= 0; when "01" => r_RESULT_int <= 1; when "10" => r_RESULT_int <= 2; when "11" => r_RESULT_int <= 3; when others => r_RESULT_int <= 0; end case; end process P_CONCATENATE; r_VAL_1_sl <= i_a_sl; r_VAL_2_sl <= i_b_sl; o_b_slv <= std_logic_vector(to_unsigned(r_RESULT_int,2)); END;