[Basic VHDL] Fully Synchronous counter ( Bộ cộng đồng bộ 8 bít )

Here, we implement a 8-bit counter which has 4 controls input: clear, load, enable, and carry. All the states can be changed at the rising clock edge.

Specification:
if clear = 1 => the output is reset to 0;
if load = 1 => the input will be loaded to the output q;
if enable = 1 and carry = 1 => the output will be increased at every single clk.
      => if carry =1, then the carry out Cout will be calculated.



Block view:

VHDL code:

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-- mathhoang entity counter is generic(width: integer := 8); port( clk,load,clear,enable,carry: in std_logic; d: in std_logic_vector(width-1 downto 0); q: out std_logic_vector(width-1 downto 0); cout: out std_logic ); end counter; architecture Behavioral of counter is signal qout: std_logic_vector(width-1 downto 0); begin q <= qout; cout <= qout(0) and qout(1) and qout(2) and qout(3) and carry; process(clk) begin if(clk'event and clk = '1') then if(clear = '1') then qout <= X"00"; elsif(load = '1') then qout <= d; elsif((enable and carry) = '1') then qout <= qout + 1; end if; end if; end process; end Behavioral;

Testing Result:

(click to enlarge the view)

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