[Basic VHDL] Basic difference between signal and variable

There are some differences between signal and variable, but we just need to keep in mind the following basic differences:
+ Variables can only be used inside processes
+ Variables are assigned using the := assignment symbol; signals are assigned using the <= assignment symbol.
+ variables immediately take the value of their assignment; but, signal is going to take the value at the next clock cycle.

Let's take a look below VHDL code and testing result. We can see that the signal o_output_1_sl is asserted at the 16th clock cycle, while the signal o_output_2_sl is asserted at the 15th clock cycle.

VHDL code

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; entity signal_variable_test is port( --i_input_slv: in std_logic_vector(7 downto 0); i_clk_sl: in std_logic; o_output_1_sl: out std_logic; o_output_2_sl: out std_logic ); end signal_variable_test; architecture Behavioral of signal_variable_test is signal r_signal_tmp_slv: std_logic_vector(7 downto 0) := (others => '0'); begin PRO_SIGNAL_TEST: process(i_clk_sl) is variable r_variable_tmp_slv: std_logic_vector(7 downto 0) := (others => '0'); begin if rising_edge(i_clk_sl) then r_signal_tmp_slv <= r_signal_tmp_slv + 1; r_variable_tmp_slv := r_variable_tmp_slv + 1; -- signal is going to take the value at the next clock cycle if(r_signal_tmp_slv = X"0F") then -- 1111 o_output_1_sl <= '1'; else o_output_1_sl <= '0'; end if; -- variables immediately take the value of their assignment if(r_variable_tmp_slv= X"0F") then o_output_2_sl <= '1'; else o_output_2_sl <= '0'; end if; end if; end process PRO_SIGNAL_TEST; end Behavioral;

Testing Result:

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