[Basic VHDL] Type Conversion / Chuyển đổi kiểu dữ liệu

1- Automatic Type conversion:
Elements of signed, unsigned, and std_logic_vector can be converted automatically to std_ulogic or std_logic.

For example,

x1_std_logic <= y1_std_logic_vector(1);
x2_std_logic <= y2_unsigned(3);



2- Type Casting:
In VHDL, we can do type casting between unsigned,signed <==> std_logic_vector

For example,

x1_std_logic_vector <= unsigned(y1_unsigned);
x2_unsigned <= std_logic_vector(y2_std_logic_vector);


3- Type Conversions:
3.1- Numeric_std:
- In numeric_std package, we can use the function TO_INTEGER() and TO_SIGNED/TO_UNSIGNED() to convert between integer and unsigned/signed numer.

For example,
integer_nbr_1 <= to_integer(unsigned_nbr);
integer_nbr_2 <= to_integer(signed_nbr);

unsigned_nbr_1 <= to_unsigned(integer_nbr);

3.2- std_logic_arith:
- In std_logic_arith package, we can use the function CONV_INTEGER() and CONV_UNSIGNED/CONV_SIGNED to convert between integer and unsigned/signed number.

4- The conversion between std_logic_vector and integer.

• std_logic_vector ==> integer 

          we should go through 2 steps:
                step1: cast std_logic_vector to unsigned/signed number
                step2: use function to_integer() to convert unsigned/signed to integer

         for example:
             int_nbr <= to_integer(unsigned(std_logic_vector_nbr));

• integer ==> std_logic_vector

         we also go through 2 steps:
             step1: use function to_unsigned()/to_signed() to convert integer number to signed/unsigned number.
             step2: case signed/unsigned number to std_logic_vector

       for example:
          std_logic_vector_nbr <= std_logic_vector(to_unsigned(unsigned_nbr, 8);