Basic notes for high-level VHDL

VHDL notes for high-level design VHDL


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-------------------------------------------------
--System-level VHDL: Package, Component
--function, procedure
package my_package is --package declaration
 type matrix is array (1 to 3, 1 to 3) of BIT;
 signal x: matrix;
 constant max1: integer := 255;
end package
package my_pkg is
 constant flag: std_logic;
 function down_edge(signal s: std_logic) return boolean;
end my_pkg;
-------
package body my_pkg is
 constant flag: std_logic :='1';
 function down_edge(signal s: std_logic) return boolean is
 begin
  return (s'event and s = '0');
 end down_edge;
end my_pkg;
--use in the project
use work.my_pgk.all;
----------- component ---------
component nand3 is
 port(a1,a2,a3: in std_logic; b: out std_logic);
end component
nand_gate: nand3 port map(x1,x2,x3,y);
nand_gate2: nand3 port map(a1=>x1,a2=>x2,a3=>x3,b=>y);
-----------
component and_gate is
 generic(n: positive := 8);
 port(a: in bit_vector(1 to n); b: out bit);
end component;
a1: and_gate generic map(16) port map(x,y);
a2: and_gate generic map(n => 16) port map(a=>x,b=>y);
---------- configuration -----
Entity test ...
end test;

architecture arch1...
end arch1;

architecture arch2...
end arch2;

configuration config1 of test is
 for arch1
 end for;
end configuration;
-------BLOCK-----------
--for: code partition: easy to read and organized
Controller: BLOCK --used inside the architecture
begin
 -- concurrent statements
end block controller;
-----
--guarded expression is true to allow the statement
--inside the block can be evaluated
blk: block(clk='1') begin
 a <= guarded d;
end block blk;
-------subprogram: function & procedure ----
--similiar to PROCESS, only sequential code are allowed
--if, wait, loop, case
assert(a'length=b'length)
 report "mismatch" & " error" &
   "checking" & " testing"
 severity failure;
 --failure|error|warning|note
--- function: sequential code only ---
function positive_edge(signal s: std_logic) return boolean is
--declare variables
begin
 return(s'event and s='1');
end function;
--used in: package,entity, architecture,process,block
--common defined in package (for libraries)
package my_subprogram is
 function positive_edge(signal s: std_logic) return boolean;
end package;
package body my_subprogram is
 function positive_edge(signal s: std_logic) return boolean
 begin
  return (s'event and s='1');
 end function;
end package body;
--function call
if positive_edge(clk) then...
--positional mapping vs. nominal mapping
my_function(x1,x2); -- positional mapping
my_function(a=>x1,b=>x2); -- nominal mapping
---------
--procedure: return more than 1 value 
package my_subprog is
 procedure min_max(signal a,b,c: in integer;
       signal min,max: out integer);
end package;

package body my_subprog is
 procedure min_max(signal a,b,c: in integer range 0 to 255;
       signal min,max: in integer range 0 to 255)
 is begin
   ....
 end procedure;
end my_subprog;
--overloaded function
function "+"(a,b: std_logic_vector) return std_logic_vector is
--declare
begin

end function "+";
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Basic notes for circuit-level VHDL

A basic notes by example for VHDL 



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------------------Standard data type-------------------
Signal a: BIT;
signal a: BIT_VECTOR(7 downto 0);
Signal a: BOOLEAN; --true & false
Signal a: BOOLEAN_VECTOR(7 downto 0);
-- -(2^31 -1) --> (2^31-1)
Signal a: integer range 0 to 15; -- -2ti -> 2ti
Signal a: natural range 0 to 15; -- 0 -> 2ti (32 bit)
signal a: positive range 1 to 16; -- 1 -> 2 ti (32 bit)
(integer_vector: VHDL 2008)
signal a: character; -- 'a','b','c',..,'NUL',
signal a: string(1 to 4); -- "VHDL"
--other type: REAL, REAL_VECTOR, TIME, TIME_VECTOR
--------------Standard-logic data type------------------
-- U,X,0,1,Z,W,L,H,-  : -: don't care
signal a: std_logic;
signal a: std_logic_vector(15 downto 0);
------------------ Signed/Unsigned ---------------------
signal a: signed(7 downto 0);
-----------------------Operators------------------------
NOT, AND, NAND, OR, NOR, XOR, XNOR
+,-,*,/, abs, rem, mod, add_carry
=,/=,>,<,>=,<=,maximum, minimum
sll,srl,sla,sra,ror,rol -- x ssl a --a: integer
shift_left,shift_right
to_unsigned, to_signed, to_slv (to_stdlogicvector),
to_integer,to_real, to_string
concatenation: &
others => '0';
--Note: numeric_bit: unsigned/signed(base=BIT)
--Note: numeric_std: unsigned/signed(base=std_logic)
---------------User-Defined Scalar Type-------------------
Type temperature is range 0 to 273; --integer types
Type state IS (S0,S1,S2); -- enumerated type
signal a: temperature;
signal state: machine_state;
---------------User-Defined Array Type-------------------
Type int_type1 is array (positive range <>) of integer;
constant const1: int_type1(1 to 4):=(1,2,3,4,5);
Type int_type2 is array(1 to 2) of int_type1;
constant const2: int_type2(1 to 2) :=((1,2,3,4),(2,3,4,5));
Type enu_type1 is array(7 downto 0) of std_logic;
constant const3: enu_type1 := ("10101010");
Type enu_type2 is array(1 to 4) of std_logi_vector(7 downto 0);
Type enu_type3 is array(1 to 3, 1 to 4) of BIT;
constant const4: enu_type3 := (("0000","0000","1111"));
--------Record: collection of different types------------
Type memory_access is record
 address_: integer range 0 to 255;
 block_: integer range 0 to 3;
 data: bit_vector(15 downto 0);
end record;
variable a: memory_access:=(12,1,X"0000");
a.address_ = 13;
------------------- Type conversions ----------------------
--qualified expression: resolve ambiguous situations
sum <= a + unsigned'(1000); --type_name'(expression)
sig <= signed(slv); --type casting
slv <= std_logic_vector(sig); -- type casting: unsigned
-- std_logic_vector <-> signed/unsigned <-> integer
---------------------- Attribute  -------------------------
'LEFT; 'RIGHT;'LOW;'HIGH; 'EVENT; 'POS; 'RANGE;'LENGTH
-------------------concurrent statements--------------------
x <=  '0' when rst = '0' else
  '1' when rst = '0' and a = '1' else
  '-'; --dont' care
with control select
 x <=  '0' when '0',
   '1' when '1',
   'z' when others;
gen: for i in 0 to 7 generate  
  x(i) <= a(i) XOR b(i);
end generate;

gen: if a=b generate
end generate;
-------------------sequential statements--------------------
if condition then
 ...
elsif (...) then
 ...
else
end if;

case data is
 when "000" => count := count + 1;
 when "001" => count := count + 2;
 when others => count := 0;
end case;

clk'event and clk = '1'
wait until (clk'event and clk = '1') --wait until condition;
wait on clk; --wait on sensitivity_list;
wait for 10 ns;
loop -- unconditional loop
 wait until clk ='1';
 count := couint + 1;
end loop;

for i in 0 to 5 loop -- i in data'range loop
 count := count + 1;
end loop;

while (i < 10) loop
 count := count + 1;
end loop;

EXIT; --exit when condition
next when i=skip; -- next when condition
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