VHDL notes for high-level design VHDL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 | ------------------------------------------------- --System-level VHDL: Package, Component --function, procedure package my_package is --package declaration type matrix is array (1 to 3, 1 to 3) of BIT; signal x: matrix; constant max1: integer := 255; end package package my_pkg is constant flag: std_logic; function down_edge(signal s: std_logic) return boolean; end my_pkg; ------- package body my_pkg is constant flag: std_logic :='1'; function down_edge(signal s: std_logic) return boolean is begin return (s'event and s = '0'); end down_edge; end my_pkg; --use in the project use work.my_pgk.all; ----------- component --------- component nand3 is port(a1,a2,a3: in std_logic; b: out std_logic); end component nand_gate: nand3 port map(x1,x2,x3,y); nand_gate2: nand3 port map(a1=>x1,a2=>x2,a3=>x3,b=>y); ----------- component and_gate is generic(n: positive := 8); port(a: in bit_vector(1 to n); b: out bit); end component; a1: and_gate generic map(16) port map(x,y); a2: and_gate generic map(n => 16) port map(a=>x,b=>y); ---------- configuration ----- Entity test ... end test; architecture arch1... end arch1; architecture arch2... end arch2; configuration config1 of test is for arch1 end for; end configuration; -------BLOCK----------- --for: code partition: easy to read and organized Controller: BLOCK --used inside the architecture begin -- concurrent statements end block controller; ----- --guarded expression is true to allow the statement --inside the block can be evaluated blk: block(clk='1') begin a <= guarded d; end block blk; -------subprogram: function & procedure ---- --similiar to PROCESS, only sequential code are allowed --if, wait, loop, case assert(a'length=b'length) report "mismatch" & " error" & "checking" & " testing" severity failure; --failure|error|warning|note --- function: sequential code only --- function positive_edge(signal s: std_logic) return boolean is --declare variables begin return(s'event and s='1'); end function; --used in: package,entity, architecture,process,block --common defined in package (for libraries) package my_subprogram is function positive_edge(signal s: std_logic) return boolean; end package; package body my_subprogram is function positive_edge(signal s: std_logic) return boolean begin return (s'event and s='1'); end function; end package body; --function call if positive_edge(clk) then... --positional mapping vs. nominal mapping my_function(x1,x2); -- positional mapping my_function(a=>x1,b=>x2); -- nominal mapping --------- --procedure: return more than 1 value package my_subprog is procedure min_max(signal a,b,c: in integer; signal min,max: out integer); end package; package body my_subprog is procedure min_max(signal a,b,c: in integer range 0 to 255; signal min,max: in integer range 0 to 255) is begin .... end procedure; end my_subprog; --overloaded function function "+"(a,b: std_logic_vector) return std_logic_vector is --declare begin end function "+"; |
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