[Basic VHDL] arithmetic operation

One of the common errors that many beginners will experience at the first time when they use vhdl is:: ERROR:HDLCompiler:1731 which means that : found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+". Let see what the root cause of this error is and how to fix it:

In VHDL, we cannot use arithmetic operation on std_logic or std_logic_vector data type directly. Let consider below code snippet:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity basic is generic(width: integer:=8); port( a: in std_logic_vector(width - 1 downto 0); b: in std_logic_vector(width - 1 downto 0); y: out std_logic_vector(width - 1 downto 0) ); end basic; architecture Behavioral of basic is begin y <= a + b; end Behavioral;

The compiler will produce an error message while compiling above code snippet. The error is something like:
found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
It means that we cannot directly use addition operation on std_logic_vector. To overcome this error, we can include std_logic_unsigned package. with this package, the addition operation will treat std_logic_vector as unsigned number, then we can do arithmetic operations on it such as: +,-,/....

Above code can be modified as below:

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-- mathHoang library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; entity basic is generic(width: integer:=8); port( a: in std_logic_vector(width-1 downto 0); b: in std_logic_vector(width-1 downto 0); y: out std_logic_vector(width-1 downto 0) ); end basic; architecture Behavioral of basic is begin y <= a + b; end Behavioral;

One more thing is that it doesn't matter if a and b don't have the same length. For example, a can be declared as std_logic_vector with 8 bits, and b is a std_logic_vector with 5 bits. The compiler will automatically call a subroutine to do a zero-extension for b to 8 bits.

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