[Basic VHDL] Type Conversion Functions

VHDL is a very strong-type language, it means that we must supply the arguments of exactly right type to a function or operator. Otherwise, the compiler will give an error message.

Although many functions or operators are overloaded so that you can use the same functions for more than one type of data, in many cases it is a must to do a type conversion.

Many type conversions can be found in the package std_logic_arith in ieee library. Mostly we deal with std_logic_vector, unsigned and integer type.

Below are some common conversion functions, we should memorize because of its convenience:

std_logic_vector to  unsigned: unsigned(x)

std_logic_vector to integer: conv_integer(x)

unsigned to std_logic_vector: std_logic_vector(x)

unsigned to integer: conv_integer(x)

integer to unsigned: conv_unsigned(x,len)

integer to std_logic_vector: conv_std_logic_vector(x,leng)

std_logic_vector to integer: to_integer(unsigned(x));


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