Teknikal-Notes

Learning new thing fast strategies

Skill and Time are two essentials for learning anything new. So the author suggests us to dedicate just twenty hours to a thing which you want to learn. This will help us come out of the frustration barrier which restrains us from experimenting with something new.

“the best thing that can happen to a human being is to find a problem, to fall in love with that problem, and to live trying to solve that problem unless another problem even more lovable appears”. The more excited, caring and focused we are on the skill we want to acquire, the more quickly we’ll acquire it.

What needs to be noted here is we are shooting for capacity and sufficiency at maximum speed and not perfection.

Five steps to learn anything fast are:Set Target Performance Level,Deconstruction of Skill,Research Just Enough,Remove Barriers,Pre-commit 20 hours per week of Practice

BaNaNa

How Js pronounces Banana:
console.write("Ba" + ("B"-"a") + "a");

Insert Node into the end of list

struct node{
    int data;
    struct node *next;
};

struct node *getLastNode(struct node *head);

void insertNode(struct node **head, int data)
{

    struct node *newNode = (struct node*)malloc(sizeof(struct node));
    newNode->next = NULL;
    newNode->data = data;
    if(*head == NULL)
    {
        *head = newNode;
    }
    else
    {
        getLastNode(*head)->next = newNode;
    }
}

struct node *getLastNode(struct node *head)
{
    struct node *lastNode = head;
    if(head == NULL)
        return NULL;
    else{
        while(lastNode->next != NULL)
            lastNode = lastNode->next;
    }
    return lastNode;
}

Remove Node with Key

struct node{
    int data;
    struct node *next;
};

void removeNodeWithData(struct node **head, int removeData)
{
    struct node *current = *head;
    struct node *prev=*head;
    while(current->data == removeData) //head
    {
        *head = (*head)->next;
        free(current);
        current = *head;
    }

    prev = *head;
    current = (*head)->next;
    while(current != NULL)
    {
        if(current->data == removeData)
        {
            prev->next = current->next;
            free(current);
        }
        else{
            prev = current;

        }
        current = prev->next;
    }

}

[Python] Basic Encoder/Decoder with Caesar CIpher

def CaesarCiper(str_,DeEn, key):
    a_=[]
    for i in str_:
        if(DeEn == "D"):
            a_.append(ord(i) - key)
        else:
            a_.append(ord(i) + key)
    def_=""
    for j in a_:
        def_ = def_ + chr(j)
    return def_

>>> a = CaesarCiper("This is a test with long sentence for Decode/Encode the message","E",2)
>>> a
'Vjku"ku"c"vguv"ykvj"nqpi"ugpvgpeg"hqt"Fgeqfg1Gpeqfg"vjg"oguucig'
>>> b = CaesarCiper(a,"D",2)
>>> b
'This is a test with long sentence for Decode/Encode the message'

[Python 1] Basic Python

Assuming that the traits of a person can be determined by a number which is a summarization of the values in their name. For example, if a = 1, b = 2, c = 3, etc. then, the name Mathhoang would be 87.

A small snippet python can be:

def calTraits():
 input_ = input("enter name: ").lower()
 sum_ = 0
 for i in input_:
  sum_ = sum_ + (ord(i) - 96)
 return sum_

another way for it:

1	sum([(ord(i) - 96) for i in input("enter name:").lower()])

The examples show that we can use python in many differnt ways to implement your ideas!

Basic notes for high-level VHDL

VHDL notes for high-level design VHDL

-------------------------------------------------
--System-level VHDL: Package, Component
--function, procedure
package my_package is --package declaration
 type matrix is array (1 to 3, 1 to 3) of BIT;
 signal x: matrix;
 constant max1: integer := 255;
end package
package my_pkg is
 constant flag: std_logic;
 function down_edge(signal s: std_logic) return boolean;
end my_pkg;
-------
package body my_pkg is
 constant flag: std_logic :='1';
 function down_edge(signal s: std_logic) return boolean is
 begin
  return (s'event and s = '0');
 end down_edge;
end my_pkg;
--use in the project
use work.my_pgk.all;
----------- component ---------
component nand3 is
 port(a1,a2,a3: in std_logic; b: out std_logic);
end component
nand_gate: nand3 port map(x1,x2,x3,y);
nand_gate2: nand3 port map(a1=>x1,a2=>x2,a3=>x3,b=>y);
-----------
component and_gate is
 generic(n: positive := 8);
 port(a: in bit_vector(1 to n); b: out bit);
end component;
a1: and_gate generic map(16) port map(x,y);
a2: and_gate generic map(n => 16) port map(a=>x,b=>y);
---------- configuration -----
Entity test ...
end test;

architecture arch1...
end arch1;

architecture arch2...
end arch2;

configuration config1 of test is
 for arch1
 end for;
end configuration;
-------BLOCK-----------
--for: code partition: easy to read and organized
Controller: BLOCK --used inside the architecture
begin
 -- concurrent statements
end block controller;
-----
--guarded expression is true to allow the statement
--inside the block can be evaluated
blk: block(clk='1') begin
 a <= guarded d;
end block blk;
-------subprogram: function & procedure ----
--similiar to PROCESS, only sequential code are allowed
--if, wait, loop, case
assert(a'length=b'length)
 report "mismatch" & " error" &
   "checking" & " testing"
 severity failure;
 --failure|error|warning|note
--- function: sequential code only ---
function positive_edge(signal s: std_logic) return boolean is
--declare variables
begin
 return(s'event and s='1');
end function;
--used in: package,entity, architecture,process,block
--common defined in package (for libraries)
package my_subprogram is
 function positive_edge(signal s: std_logic) return boolean;
end package;
package body my_subprogram is
 function positive_edge(signal s: std_logic) return boolean
 begin
  return (s'event and s='1');
 end function;
end package body;
--function call
if positive_edge(clk) then...
--positional mapping vs. nominal mapping
my_function(x1,x2); -- positional mapping
my_function(a=>x1,b=>x2); -- nominal mapping
---------
--procedure: return more than 1 value 
package my_subprog is
 procedure min_max(signal a,b,c: in integer;
       signal min,max: out integer);
end package;

package body my_subprog is
 procedure min_max(signal a,b,c: in integer range 0 to 255;
       signal min,max: in integer range 0 to 255)
 is begin
   ....
 end procedure;
end my_subprog;
--overloaded function
function "+"(a,b: std_logic_vector) return std_logic_vector is
--declare
begin

end function "+";

Basic notes for circuit-level VHDL

A basic notes by example for VHDL

------------------Standard data type-------------------
Signal a: BIT;
signal a: BIT_VECTOR(7 downto 0);
Signal a: BOOLEAN; --true & false
Signal a: BOOLEAN_VECTOR(7 downto 0);
-- -(2^31 -1) --> (2^31-1)
Signal a: integer range 0 to 15; -- -2ti -> 2ti
Signal a: natural range 0 to 15; -- 0 -> 2ti (32 bit)
signal a: positive range 1 to 16; -- 1 -> 2 ti (32 bit)
(integer_vector: VHDL 2008)
signal a: character; -- 'a','b','c',..,'NUL',
signal a: string(1 to 4); -- "VHDL"
--other type: REAL, REAL_VECTOR, TIME, TIME_VECTOR
--------------Standard-logic data type------------------
-- U,X,0,1,Z,W,L,H,-  : -: don't care
signal a: std_logic;
signal a: std_logic_vector(15 downto 0);
------------------ Signed/Unsigned ---------------------
signal a: signed(7 downto 0);
-----------------------Operators------------------------
NOT, AND, NAND, OR, NOR, XOR, XNOR
+,-,*,/, abs, rem, mod, add_carry
=,/=,>,<,>=,<=,maximum, minimum
sll,srl,sla,sra,ror,rol -- x ssl a --a: integer
shift_left,shift_right
to_unsigned, to_signed, to_slv (to_stdlogicvector),
to_integer,to_real, to_string
concatenation: &
others => '0';
--Note: numeric_bit: unsigned/signed(base=BIT)
--Note: numeric_std: unsigned/signed(base=std_logic)
---------------User-Defined Scalar Type-------------------
Type temperature is range 0 to 273; --integer types
Type state IS (S0,S1,S2); -- enumerated type
signal a: temperature;
signal state: machine_state;
---------------User-Defined Array Type-------------------
Type int_type1 is array (positive range <>) of integer;
constant const1: int_type1(1 to 4):=(1,2,3,4,5);
Type int_type2 is array(1 to 2) of int_type1;
constant const2: int_type2(1 to 2) :=((1,2,3,4),(2,3,4,5));
Type enu_type1 is array(7 downto 0) of std_logic;
constant const3: enu_type1 := ("10101010");
Type enu_type2 is array(1 to 4) of std_logi_vector(7 downto 0);
Type enu_type3 is array(1 to 3, 1 to 4) of BIT;
constant const4: enu_type3 := (("0000","0000","1111"));
--------Record: collection of different types------------
Type memory_access is record
 address_: integer range 0 to 255;
 block_: integer range 0 to 3;
 data: bit_vector(15 downto 0);
end record;
variable a: memory_access:=(12,1,X"0000");
a.address_ = 13;
------------------- Type conversions ----------------------
--qualified expression: resolve ambiguous situations
sum <= a + unsigned'(1000); --type_name'(expression)
sig <= signed(slv); --type casting
slv <= std_logic_vector(sig); -- type casting: unsigned
-- std_logic_vector <-> signed/unsigned <-> integer
---------------------- Attribute  -------------------------
'LEFT; 'RIGHT;'LOW;'HIGH; 'EVENT; 'POS; 'RANGE;'LENGTH
-------------------concurrent statements--------------------
x <=  '0' when rst = '0' else
  '1' when rst = '0' and a = '1' else
  '-'; --dont' care
with control select
 x <=  '0' when '0',
   '1' when '1',
   'z' when others;
gen: for i in 0 to 7 generate  
  x(i) <= a(i) XOR b(i);
end generate;

gen: if a=b generate
end generate;
-------------------sequential statements--------------------
if condition then
 ...
elsif (...) then
 ...
else
end if;

case data is
 when "000" => count := count + 1;
 when "001" => count := count + 2;
 when others => count := 0;
end case;

clk'event and clk = '1'
wait until (clk'event and clk = '1') --wait until condition;
wait on clk; --wait on sensitivity_list;
wait for 10 ns;
loop -- unconditional loop
 wait until clk ='1';
 count := couint + 1;
end loop;

for i in 0 to 5 loop -- i in data'range loop
 count := count + 1;
end loop;

while (i < 10) loop
 count := count + 1;
end loop;

EXIT; --exit when condition
next when i=skip; -- next when condition
-------------------------------------------------

[VHDL] Good math tricks source for VHDL

http://www.gstitt.ece.ufl.edu/vhdl/refs/vhdl_math_tricks_mapld_2003.pdf

Những điểm mạnh và yếu của SPI (Serial Peripheral Interface)

Advantages of SPI

1. Full duplex communication
2. Higher throughput than I²C protocol
3. Not limited to 8-bit words in the case of bit-transferring
4. Arbitrary choice of message size, contents, and purpose
5. Simple hardware interfacing
6. Typically lower power requirements than I²C due to less circuitry.
7. No arbitration or associated failure modes.
8. Slaves use the master's clock, and don't need precision oscillators.
9. Transceivers are not needed.
10. At most one "unique" bus signal per device (CS); all others are shared

Disadvantages of SPI

1. Requires more pins on IC packages than I²C
2. No in-band addressing. Out-of-band chip select signals are required on shared busses.
3. No hardware flow control
4. No slave acknowledgment
5. Multi-master busses are rare and awkward, and are usually limited to a single slave.
6. Without a formal standard, validating conformance is not possible
7. Only handles short distances compared to RS-232, RS-485, or CAN.

Words!!!

Old Sayings

"Ngủ dậy muộn thì phí mất cả ngày, ở tuổi thanh niên mà không học tập thì phí mất cả cuộc đời." __ Ngạn ngữ Trung Quốc

"Nếu ta không gieo trồng tri thức khi còn trẻ, nó sẽ không cho ta bóng râm khi ta về già." __ Chesterfield

[Easy Data Structure] Nice functions to traverse and find middle node in Singly Linked List

#include
#include

struct ListNode * InitLinkedList();
int PrintFromBeginning(struct ListNode *head);
int CheckOddorEvenLength(struct ListNode *head);
struct ListNode *FindMiddleNode(struct ListNode *head);

//#define NULL 0
struct ListNode{
int data;
struct ListNode *next;
};

struct ListNode * InitLinkedList()
{
struct ListNode *head = malloc(sizeof(struct ListNode));
struct ListNode *node1, *node2, *node3, *node4;
struct ListNode *newNode = malloc(sizeof(struct ListNode));

node2 = malloc(sizeof(struct ListNode));
node3 = malloc(sizeof(struct ListNode));
node4 = malloc(sizeof(struct ListNode));

head->data = 1;
head->next = NULL;

node1 = head;
node1->next = node2;

node2->data = 2;
node2->next = node3;

node3->data = 3;
node3->next = node4;

node4->data = 4;
node4->next = newNode;

newNode->data = 5;
newNode->next = NULL;

return head;
}

int PrintFromBeginning(struct ListNode *head)
{
if(!head)
return 0;
else
{
printf("| %d |",head->data);
return PrintFromBeginning(head->next);
}
}

int CheckOddorEvenLength(struct ListNode *head)
{
if(!head)
return 0;
else
{
return (1 + CheckOddorEvenLength(head->next))%2;
}
}

struct ListNode *FindMiddleNode(struct ListNode *head)
{
struct ListNode *ptr1x, *ptr2x;
int i = 0;
ptr1x = ptr2x = head;
while(ptr1x->next)
{
if(i == 0)
{
ptr1x = ptr1x->next;
i = 1;
}
else
{
ptr1x = ptr1x->next;
ptr2x = ptr2x->next;
i = 0;
}
}
return ptr2x;
}
/* run this program using the console pauser or add your own getch, system("pause") or input loop */
int main(int argc, char *argv[]) {
struct ListNode *head = InitLinkedList();
PrintFromBeginning(head);
if(CheckOddorEvenLength(head))
printf("\n-- Odd---");
else
printf("\n--- Even---");

printf("\n---Middle node: %d",FindMiddleNode(head)->data);

return 0;
}

---
Hàm cơ bản trong linked list dùng hàm đệ quy

Circular Array

Circular Array = Circular Buffer = Cyclic Buffer = Ring Buffer

The magic behind Circular Array is the operator: Mod

[HW] Why do we need to separate data cache and instruction cache?

There are actually several reasons.

First and probably foremost, the data that's stored in the instruction cache is generally somewhat different than what's stored in the data cache -- along with the instructions themselves, there are annotations for things like where the next instruction starts, to help out the decoders. Some processors (E.g., Netburst, some SPARCs) use a "trace cache", which stores the result of decoding an instruction rather than storing the original instruction in its encoded form.

Burning the Bootloader on ATMega328 using Arduino UNO

(Tải bootloader lên Arduino)

Burning a bootloader to an atmega328P or atmega328 using Arduino Uno version 1.6.5 or later is now easier than ever.

Step1: open and upload the sketch ArduinoISP to atmega328P on your Arduino board( without connection with another atmega328P )

Câu hỏi cơ bản thường gặp trong lập trình nhúng

1. What are static variables?

Static variable in a function only remain one copy of itself.
Static variable in a module can be used by any function in the module
Static function can only be called in its class

2. What are volatile variables?
Volatile variables may change its value unexpectedly in the program.
The program will check its value every time, it tries to use it.
If a variable is not volatile, the program may keep a copy of the var in its cache.

3. What do you mean by const keyword ?
A constant variable is a read only variable. You cant change its value else where except initialization.

4. What is interrupt latency?
Interrupt latency is the time between the generation of interrupt and the time for interrupt handler to process it.

5. How you can optimize it?
We may use polling and message passing for interrupt to handle interrupt immediately.

[ref from: http://bobselectronics.blogspot.com/2014/07/sainsmart-hall-effect-sensor-board.html]

Sainsmart Hall Effect Sensor board

This is a very simple description of how this board works. I was unable to find this info on the internet nor was the company I bought the board from any help.
This is a very inexpensive pre-assembled hall effect sensor available on EBAY that provides both a digital and analog output that is easily incorporated into the Arduino as a RPM measurement tool.
There are 4 connections: + is +5V, - is ground, AO is analog out and DO is digital out.
A 10K pull up resistor is needed between which ever output is used and +5V. This will keep the DO at high when no magnetic influence is detected. When a magnetic field is detected the DO pin will go low and this can be inputted to one of the Arduino digital input pins. There are two red LEDs on the board. The lower left one is on when power is supplied to the board and the lower right is on when DO goes low. If the lower right is on with no magnetic field then the variable pot must be adjusted until it goes out.
The analog output varies from 0 to +2.5V.
There are several Arduino sketches for using a hall effect sensor available on the internet but they have poor low RPM accuracy and I made a few modifications that I will post when I have a little time. I use a Sainsmart LCD keypad shield on the Arduino and it displays the RPM as a self contained unit.

Here is a link to a diagram of the Eagle layout:
https://drive.google.com/file/d/0BxCQZLsb0vTKQndodjFrUVJqRFU/edit?usp=sharing

[Arduino] Build error on Arduino Eclipse plugin

If you get the following error while building an ARduino UNO application on Eclipse:

"make all
Cannot run program "make": Launching failed
Error: Program "make" not found in PATH"

Then, you can fix it by including the makefile program path into environment variable PATH.

The fix can be as below:

Step1: if you have not had makefile on your computer yet, then you can install: MinGW_Toolchains.
It can be downloaded from:
http://sourceforge.net/projects/mingw-w64/files/latest/download?source=files

Step2: Assuming that you had installed MinGW_Toolchains into drive C, now you can add the path: C:\MinGW_Toolchains\mingw64\bin into your PATH variable environment.

You can update this PATH variable environment via Eclipse as below:
From Eclipse: Window --> Preferences --> C/C++ --> Environment

Variable PATH will be there, then you can update the PATH similarly as following:

Scheduling algorithm

This is an implementation of ASAP scheduling algorithm, ALAP scheduling algorithm and LIST_L scheduling algorithm.

It is assumed that:
    + ALU will do the arithmetical operations: +, -, >,<, etc.
  + Multiplier: *
  + Divisor: /

LIST_L scheduling algorithm: (adjusted from the book: Synthesis and Optimizations of Digital Circuits by Giovanni De Micheli)

{

Repeat until all vertices determined {

Determined the distance label between vertex V_iand sink;

}

Repeat until all non-leaf vertices are scheduled: {

Repeat for each source type

{

Determine ready vertices U;

Determine unfinished vertices T;

Select S Є U;

Schedule S at clock cycle l;

}

l = l + 1;

}

return (t);

}