Teknikal-Notes

[Xilinx] Simulation Runtime: How to change default simulation run time

Default simulation run time in Xilinx is 1000ns. Sometimes, we need a bigger time frame to run our simulation. We can easily change this default value into our desired value. It can be done either by ISIM command or window GUI setting.

Below is one of the easy ways to change default simulation run time. ( simulation time )

Step1: From your main working workspace, choose the option "Simulation"

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Step 2: Right click on Simulate Behavioral Model, then choose Process Properties...

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Step 3 : change the default vaule 1000 ns in texbox Simulation Run Time to your expected value:

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Xilinx, Tutorial, Change the simulation run time, Simulation time

[Basic VHDL] Signal Assignments: with/select ; when/else; case/when

In vhdl, we usually can do the same things in different ways; and, signal assignment is one of the them. There are basically 3 ways to do it. They are look kinda similar and not easy to remember. Let's take a look at these signal assignments.

1- with .... select ..... when
with/select is called officially "selected signal assignment" in vhdl. below is an example of this signal assignment:

 with op select
 
 controls y <= "110000010" when "000000",
     "101001000" when "100011",
     "001010000" when "101011",
     "000100001" when "000100",
     "101000000" when "001000",
     "000000100" when "000010",
     "---------" when others;

2- When ..... else
It is officially called "conditional signal assignment" in vhdl. It seems to be a little bit more general than with/select/when. Below is an example of this signal assignment:

 y <=      "110000010" when op = "000000" else
   "101001000" when op = "100011" else
   "001010000" when op = "101011" else
   "000100001" when op = "000100" else
   "101000000" when op = "001000" else
   "000000100" when op = "000010" else
   "---------" when others;

3- Case ... when
This statement is always used inside a process. This statement is the same as IF-THEN-ELSE statement. They are equivalent.

 process(op) is begin
  case op is
   when "000000" => controls <= "110000010";
   when "100011" => controls <= "101001000";
   when "101011" => controls <= "001010000";
   when "000100" => controls <= "000100001";
   when "001000" => controls <= "101000000";
   when "000010" => controls <= "000000100";
   when others   => controls <= "---------";
  end case;
 end process;

[Xilinx] Error Fixing: model technology's vsim executable cannot be found

Whenever you have got below error while running simulation:
"model technology's vsim executable cannot be found"

It means that you need to choose a suitable simulator, there are some ways to overcome this. below is one of the easy way to fix this error ( for VHDL ):

Step1: Right click on your main file, and choose Design Properties...: